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125
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ISLPED
2000
ACM
99views Hardware» more  ISLPED 2000»
15 years 9 months ago
Practical considerations of clock-powered logic
Recovering and reusing circuit energies that would otherwise be dissipated as heat can reduce the power dissipated by a VLSI chip. To accomplish this requires a power source that ...
William C. Athas
125
Voted
ARITH
1999
IEEE
15 years 9 months ago
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition
In two operand addition, bit-wise intermediate variables such as the "propagate" and "generate" terms are defined/evaluated first. Basic carry propagation recu...
Dhananjay S. Phatak, Israel Koren
ASPDAC
1999
ACM
116views Hardware» more  ASPDAC 1999»
15 years 9 months ago
An Automatic Router for the Pin Grid Array Package
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on...
Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chi...
ASPDAC
1999
ACM
107views Hardware» more  ASPDAC 1999»
15 years 9 months ago
New Multilevel and Hierarchical Algorithms for Layout Density Control
Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on loca...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Alex...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 9 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...