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FCCM
1998
IEEE
169views VLSI» more  FCCM 1998»
15 years 8 months ago
Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application
Abstract Image processing, specifically Automatic Target Recognition (ATR) in Synthetic Aperture Radar (SAR) imagery, is an application area that can require tremendous processing ...
Ruth Sivilotti, Young Cho, Wen-King Su, Danny Cohe...
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
15 years 8 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
FCCM
1997
IEEE
199views VLSI» more  FCCM 1997»
15 years 8 months ago
The RAW benchmark suite: computation structures for general purpose computing
The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut o...
Jonathan Babb, Matthew Frank, Victor Lee, Elliot W...
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
15 years 8 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
VLSID
1996
IEEE
110views VLSI» more  VLSID 1996»
15 years 8 months ago
On test coverage of path delay faults
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...