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DATE
2006
IEEE
114views Hardware» more  DATE 2006»
15 years 10 months ago
An efficient static algorithm for computing the soft error rates of combinational circuits
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Denni...
DELTA
2006
IEEE
15 years 10 months ago
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method
In high speed digital circuits, the inductive effect is more dominant compared to capacitive effect. In particular, as the technology is shrinking, the spacing between interconnec...
K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srini...
DFT
2006
IEEE
74views VLSI» more  DFT 2006»
15 years 10 months ago
Recovery Mechanisms for Dual Core Architectures
Dual core architectures are commonly used to establish fault tolerance on the node level. Since comparison is usually performed for the outputs only, no precise diagnostic informa...
Christian El Salloum, Andreas Steininger, Peter Tu...
DFT
2006
IEEE
120views VLSI» more  DFT 2006»
15 years 10 months ago
On-Line Mapping of In-Field Defects in Image Sensor Arrays
Continued increase in complexity of digital image sensors means that defects are more likely to develop in the field, but little concrete information is available on in-field defe...
Jozsef Dudas, Cory Jung, Linda Wu, Glenn H. Chapma...
142
Voted
DFT
2006
IEEE
125views VLSI» more  DFT 2006»
15 years 10 months ago
Synthesis of Efficient Linear Test Pattern Generators
This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area,...
Avijit Dutta, Nur A. Touba