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FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
15 years 10 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
FCCM
2006
IEEE
137views VLSI» more  FCCM 2006»
15 years 10 months ago
Single Pass, BLAST-Like, Approximate String Matching on FPGAs
Abstract: Approximate string matching is fundamental to bioinformatics, and has been the subject of numerous FPGA acceleration studies. We address issues with respect to FPGA imple...
Martin C. Herbordt, Josh Model, Yongfeng Gu, Bhara...
ISCAS
2006
IEEE
152views Hardware» more  ISCAS 2006»
15 years 10 months ago
3D integrated sensors in silicon-on-sapphire CMOS
We fabricated a 3D-integrated multi-chip sensor separate dies [9]. In this paper, we present a 3D integrated and actuator and demonstrated the ability of communication with tempera...
Eugenio Culurciello, Andreas G. Andreou
ISCAS
2006
IEEE
111views Hardware» more  ISCAS 2006»
15 years 10 months ago
CMOS analog iterative decoders using margin propagation circuits
Abstract- Analog iterative decoders offer several advantages over their digital counterparts in terms of speed and power -A- log-MAP consumption. The current state of art CMOS anal...
S. Chakrabartty
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
15 years 10 months ago
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici C...