2449 search results - page 438 / 490 » VLSI |
ICCAD
2000
IEEE
15 years 2 months ago
2000
IEEE
––In this paper, a corner block list — a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block...
IJCNN
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper presents a simple continuous analog hardware realization of the Random Neural Network (RNN) model. The proposed circuit uses the general principles resulting from the u...
ASPDAC
2000
ACM
15 years 2 months ago
2000
ACM
Multilevel Fiduccia-Mattheyses MLFM hypergraph partitioning 3, 22, 24 is a fundamental optimization in VLSI CAD physical design. The leading implementation, hMetis 23 , has sinc...
ASPDAC
2000
ACM
15 years 2 months ago
2000
ACM
- This paper presents a new aged timing simulation methodology that can be used for hot-carrier reliability assurance of VLSI. This methodology consists of a compact model and a un...
DAC
2000
ACM
15 years 2 months ago
2000
ACM
—Chemical–mechanical polishing (CMP) is an enabling technique used in deep-submicrometer VLSI manufacturing to achieve long range oxide planarization. Post-CMP oxide topography...