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FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
15 years 3 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
FCCM
2005
IEEE
132views VLSI» more  FCCM 2005»
15 years 3 months ago
Hardware Factorization Based on Elliptic Curve Method
The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factorization large integers is ...
Martin Simka, Jan Pelzl, Thorsten Kleinjung, Jens ...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 3 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
ISPD
2005
ACM
151views Hardware» more  ISPD 2005»
15 years 3 months ago
Thermal via placement in 3D ICs
As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promi...
Brent Goplen, Sachin S. Sapatnekar
SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
15 years 3 months ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...