163 search results - page 3 / 33 » Variation-aware routing for FPGAs |
ISPD
2006
ACM
14 years 7 days ago
2006
ACM
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
FPGA
2003
ACM
13 years 11 months ago
2003
ACM
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
ISPD
2009
ACM
14 years 1 months ago
2009
ACM
Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routi...
FPGA
2006
ACM
13 years 10 months ago
2006
ACM
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...
FPGA
1995
ACM
13 years 9 months ago
1995
ACM
Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused...