49 search results - page 5 / 10 » Vdd programmability to reduce FPGA interconnect power |
DSD
2007
IEEE
15 years 3 months ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
CORR
2010
Springer
14 years 9 months ago
2010
Springer
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
Abstract— As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unus...
FPGA
2009
ACM
15 years 4 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...