49 search results - page 6 / 10 » Vdd programmability to reduce FPGA interconnect power |
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size...
TVLSI
2008
14 years 9 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
FPGA
2009
ACM
15 years 4 months ago
2009
ACM
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
The performance benefits of a monolithically stacked 3DFPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and...
FPGA
2010
ACM
15 years 6 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...