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116
Voted
FPL
1999
Springer
103views Hardware» more  FPL 1999»
15 years 4 months ago
IP Validation for FPGAs Using Hardware Object Technology
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
Steve Casselman, John Schewel, Christophe Beaumont
114
Voted
DAC
1996
ACM
15 years 4 months ago
Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems
-- This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us ...
Eric Verlind, Gjalt G. de Jong, Bill Lin
103
Voted
DAC
1994
ACM
15 years 4 months ago
BDD Variable Ordering for Interacting Finite State Machines
We address the problem of obtaining good variable orderings for the BDD representation of a system of interacting finite state machines (FSMs). Orderings are derived from the comm...
Adnan Aziz, Serdar Tasiran, Robert K. Brayton
CP
2006
Springer
15 years 4 months ago
A New Algorithm for Sampling CSP Solutions Uniformly at Random
The paper presents a method for generating solutions of a constraint satisfaction problem (CSP) uniformly at random. The main idea is to express the CSP as a factored probability d...
Vibhav Gogate, Rina Dechter
94
Voted
FMOODS
2006
15 years 1 months ago
Bounded Analysis and Decomposition for Behavioural Descriptions of Components
Abstract. Explicit behavioural interfaces are now accepted as a mandatory feature of components to address architectural analysis. Behavioural interface description languages shoul...
Pascal Poizat, Jean-Claude Royer, Gwen Salaün