37 search results - page 7 / 8 » Verification of Floating-Point Adders |
140
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FCCM
2007
IEEE
15 years 5 months ago
2007
IEEE
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
105
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DAC
1996
ACM
15 years 7 months ago
1996
ACM
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
120
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ASAP
2007
IEEE
15 years 5 months ago
2007
IEEE
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
GLVLSI
1999
IEEE
15 years 7 months ago
1999
IEEE
142
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FMCAD
2000
Springer
15 years 7 months ago
2000
Springer
Abstract. We present a formal verification methodology for datapathdominated hardware. This provides a systematic but flexible framework within which to organize the activities und...