In this paper, we describe a hybrid tool for hardware formal verification that links the HOL (higher-order logic) theorem prover and (multiway decision graphs) model checker. Our ...
Guidelines (Extended abstract) Ruud Stegers1 , Annette ten Teije1 , and Frank van Harmelen1 Vrije Universiteit, Amsterdam The main problem encountered when starting verification of...
Ruud Stegers, Annette ten Teije, Frank van Harmele...
In this paper, we explore the potential of the theory of nested words for partial correctness proofs of recursive programs. Our conceptual contribution is a simple framework that ...
Matthias Heizmann, Jochen Hoenicke, Andreas Podels...
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
We present a formalism for the automatic verification of security protocols based on multi-agent systems semantics. We give the syntax and semantics of a temporal-epistemic securit...