103 search results - page 16 / 21 » Verification of configurable processor cores |
88
Voted
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such appro...
TC
2008
14 years 9 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
79
Voted
ASPLOS
2008
ACM
14 years 11 months ago
2008
ACM
Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage v...
131
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MOBILIGHT
2010
14 years 7 months ago
2010
Abstract. This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a ...
DSD
2004
IEEE
15 years 1 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...