103 search results - page 6 / 21 » Verification of configurable processor cores |
98
Voted
IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...
ASAP
2007
IEEE
14 years 11 months ago
2007
IEEE
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
78
Voted
ISCAS
2003
IEEE
15 years 2 months ago
2003
IEEE
Communication synthesis is an essential step in hardware/software co-synthesis: many embedded systems use automatic generation of interface for point to point communication or use...
VL
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper shows how language technologies such as the automatic generation of parsers for analyzing user actions and visual parsing can be applied to build a flexible tool specia...
SBACPAD
2008
IEEE
15 years 4 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...