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» Verification of object-oriented simulation designs
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FMCAD
2007
Springer
15 years 3 months ago
Formal Verification of Partial Good Self-Test Fencing Structures
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
Adrian E. Seigler, Gary A. Van Huben, Hari Mony
82
Voted
SAFECOMP
2010
Springer
14 years 7 months ago
Experiences in Applying Formal Verification in Robotics
Formal verification efforts in the area of robotics are still comparatively scarce. In this paper we report on our experiences with one such effort, which was concerned with design...
Dennis Walter, Holger Täubig, Christoph L&uum...
TVLSI
2002
130views more  TVLSI 2002»
14 years 9 months ago
Incremental compilation for parallel logic verification systems
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...
R. Tessier, S. Jana
FMCAD
2006
Springer
15 years 1 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
DAC
2002
ACM
15 years 10 months ago
Deriving a simulation input generator and a coverage metric from a formal specification
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
Kanna Shimizu, David L. Dill