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» Verifying Reference Counting Implementations
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85
Voted
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
15 years 1 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
ISCA
1998
IEEE
143views Hardware» more  ISCA 1998»
15 years 1 months ago
Lockup-Free Instruction Fetch/Prefetch Cache Organization
In the past decade. there has been much literature describing various cache organizatrons that exploit general programming idiosyncrasies to obtain maxrmum hit rate (the probabili...
David Kroft
89
Voted
FPT
2005
IEEE
133views Hardware» more  FPT 2005»
15 years 3 months ago
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator
Two FPGA implementations of a Shape Adaptive Discrete Cosine Transform (SA-DCT) accelerator are presented in this paper: one PCI-based and the other AMBA-based. The former is used...
Andrew Kinane, Alan Casey, Valentin Muresan, Noel ...
77
Voted
JUCS
2008
117views more  JUCS 2008»
14 years 9 months ago
Eliminating Cycles in Weak Tables
: Weak References constitute an elegant mechanism for an application to interact with its garbage collector. In most of its typical uses, weak references are used through weak tabl...
Alexandra Barros, Roberto Ierusalimschy
ICS
2004
Tsinghua U.
15 years 2 months ago
Inter-reference gap distribution replacement: an improved replacement algorithm for set-associative caches
We propose a novel replacement algorithm, called InterReference Gap Distribution Replacement (IGDR), for setassociative secondary caches of processors. IGDR attaches a weight to e...
Masamichi Takagi, Kei Hiraki