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» Verifying VLSI Circuits

56

GLVLSI
2007
IEEE

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Analyzing and modeling process balance for sub-threshold circuit design

15 years 3 months ago

Analyzing and modeling process balance for sub-threshold circuit design

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Joseph F. Ryan, Jiajing Wang, Benton H. Calhoun

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53

GLVLSI
2003
IEEE

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MuTaTe: an efficient design for testability technique for multiplexor based circuits

15 years 2 months ago

MuTaTe: an efficient design for testability technique for multiplexor based circuits

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Rolf Drechsler, Junhao Shi, Görschwin Fey

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67

GLVLSI
2003
IEEE

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Repeater and current-sensing hybrid circuits for on-chip interconnects

15 years 2 months ago

Repeater and current-sensing hybrid circuits for on-chip interconnects

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Atul Maheshwari, Wayne Burleson

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53

GLVLSI
1999
IEEE

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Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus

15 years 1 months ago

Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus

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James C. Ellenbogen

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55

GLVLSI
1999
IEEE

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A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs

15 years 1 months ago

A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs

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Hideaki Matsuzaki, Toshihiro Itoh, Masafumi Yamamo...

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