Sciweavers

487 search results - page 13 / 98
» Versatile Imaging Architecture Based on a System on Chip
Sort
View
126
Voted
CICC
2011
106views more  CICC 2011»
13 years 11 months ago
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....
APCSAC
2006
IEEE
15 years 5 months ago
Power-Efficient Microkernel of Embedded Operating System on Chip
Because the absence of hardware support, almost all of embedded operating system are based on SDRAM in past time. With progress of embedded system hardware, embedded system can pro...
Tianzhou Chen, Wei Hu, Yi Lian
82
Voted
ICIP
1994
IEEE
16 years 1 months ago
Full Custom VLSI Implementation of High-Speed 2-D DCT/IDCT Chip
In this paper we present a full-custom VLSI design of highspeed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been i...
Vishnu Srinivasan, K. J. Ray Liu
78
Voted
SBCCI
2003
ACM
96views VLSI» more  SBCCI 2003»
15 years 4 months ago
SoCIN: A Parametric and Scalable Network-on-Chip
Networks-on-Chip (NoCs) interconnection architectures to be used in future billion-transistor Systems-on-Chip (SoCs) meet the major communication requirements of these systems, of...
Cesar Albenes Zeferino, Altamiro Amadeu Susin
IPPS
2007
IEEE
15 years 6 months ago
Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao