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» Versatile Imaging Architecture Based on a System on Chip
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NOCS
2009
IEEE
15 years 6 months ago
Scalability of network-on-chip communication architecture for 3-D meshes
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuw...
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
14 years 9 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
SIGGRAPH
1996
ACM
15 years 3 months ago
Modeling and Rendering Architecture from Photographs: A Hybrid Geometry- and Image-Based Approach
We present a new approach for modeling and rendering existing architectural scenes from a sparse set of still photographs. Our modeling approach, which combines both geometry-base...
Paul E. Debevec, Camillo J. Taylor, Jitendra Malik
ICCAD
2008
IEEE
105views Hardware» more  ICCAD 2008»
15 years 8 months ago
Parameterized transient thermal behavioral modeling for chip multiprocessors
In this paper, we propose a new architecture-level parameterized transient thermal behavioral modeling algorithm for emerging thermal related design and optimization problems for ...
Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Mur...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
16 years 4 days ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...