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ICDCS
2007
IEEE
15 years 11 months ago
STEP: Sequentiality and Thrashing Detection Based Prefetching to Improve Performance of Networked Storage Servers
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
Shuang Liang, Song Jiang, Xiaodong Zhang
206
Voted
EUROPAR
2011
Springer
14 years 4 months ago
A Bit-Compatible Parallelization for ILU(k) Preconditioning
Abstract. ILU(k) is a commonly used preconditioner for iterative linear solvers for sparse, non-symmetric systems. It is often preferred for the sake of its stability. We present T...
Xin Dong 0004, Gene Cooperman
126
Voted
IPPS
2007
IEEE
15 years 11 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
145
Voted
HIPC
1999
Springer
15 years 9 months ago
Process Migration Effects on Memory Performance of Multiprocessor
Abstract. In this work we put into evidence how the memory performance of a WebServer machine may depend on the sharing induced by process migration. We considered a shared-bus sha...
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Anton...
CCGRID
2011
IEEE
14 years 8 months ago
High Performance Pipelined Process Migration with RDMA
—Coordinated Checkpoint/Restart (C/R) is a widely deployed strategy to achieve fault-tolerance. However, C/R by itself is not capable enough to meet the demands of upcoming exasc...
Xiangyong Ouyang, Raghunath Rajachandrasekar, Xavi...