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» Visualization of Concurrent Program Executions
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FPL
2009
Springer
132views Hardware» more  FPL 2009»
15 years 3 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
ISCA
2010
IEEE
189views Hardware» more  ISCA 2010»
15 years 4 months ago
RETCON: transactional repair without replay
Over the past decade there has been a surge of academic and industrial interest in optimistic concurrency, i.e. the speculative parallel execution of code regions that have the se...
Colin Blundell, Arun Raghavan, Milo M. K. Martin
RSP
2006
IEEE
120views Control Systems» more  RSP 2006»
15 years 5 months ago
A Case Study of Design Space Exploration for Embedded Multimedia Applications on SoCs
Embedded real-time multimedia applications usually imply data parallel processing. SIMD processors embedded in SOCs are cost-effective to exploit the underlying parallelism. Howev...
Isabelle Hurbain, Corinne Ancourt, François...
ISCA
2012
IEEE
208views Hardware» more  ISCA 2012»
13 years 2 months ago
Harmony: Collection and analysis of parallel block vectors
Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effor...
Melanie Kambadur, Kui Tang, Martha A. Kim
ICLP
2005
Springer
15 years 5 months ago
Modeling Systems in CLP
We present a methodology for the modeling of complex program behavior in CLP. In the first part we present an informal description about how to represent a system in CLP. At its ...
Joxan Jaffar, Andrew E. Santosa, Razvan Voicu