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DAC
2005
ACM
16 years 22 days ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
POPL
2005
ACM
16 years 2 days ago
Transactors: a programming model for maintaining globally consistent distributed state in unreliable environments
We introduce transactors, a fault-tolerant programming model for composing loosely-coupled distributed components running in an unreliable environment such as the internet into sy...
John Field, Carlos A. Varela
SC
2009
ACM
15 years 6 months ago
Scalable temporal order analysis for large scale debugging
We present a scalable temporal order analysis technique that supports debugging of large scale applications by classifying MPI tasks based on their logical program execution order...
Dong H. Ahn, Bronis R. de Supinski, Ignacio Laguna...
TVLSI
2010
14 years 6 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
INFFUS
2006
137views more  INFFUS 2006»
14 years 11 months ago
Bipolar possibility theory in preference modeling: Representation, fusion and optimal solutions
The bipolar view in preference modeling distinguishes between negative and positive preferences. Negative preferences correspond to what is rejected, considered unacceptable, whil...
Salem Benferhat, Didier Dubois, Souhila Kaci, Henr...