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» Why Not Use a Pattern-Based Parallel Programming System
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HPDC
2007
IEEE
15 years 8 months ago
Feedback-directed thread scheduling with memory considerations
This paper describes a novel approach to generate an optimized schedule to run threads on distributed shared memory (DSM) systems. The approach relies upon a binary instrumentatio...
Fengguang Song, Shirley Moore, Jack Dongarra
112
Voted
IPPS
2008
IEEE
15 years 8 months ago
Lattice Boltzmann simulation optimization on leading multicore platforms
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of searchbased performance optimizatio...
Samuel Williams, Jonathan Carter, Leonid Oliker, J...
IPPS
2003
IEEE
15 years 7 months ago
Performance and Overhead in a Hybrid Reconfigurable Computer
In this paper, we overview general hardware architecture and a programming model of SRC-6ETM reconfigurable computers, and compare the performance of the SRC-6E machine vs. IntelĀ...
Osman Devrim Fidanci, Daniel S. Poznanovic, Kris G...
136
Voted
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 6 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
135
Voted
SIGMOD
2012
ACM
226views Database» more  SIGMOD 2012»
13 years 4 months ago
SkewTune: mitigating skew in mapreduce applications
We present an automatic skew mitigation approach for userdefined MapReduce programs and present SkewTune, a system that implements this approach as a drop-in replacement for an e...
YongChul Kwon, Magdalena Balazinska, Bill Howe, Je...