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SLIP
2006
ACM
15 years 5 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
TC
2010
14 years 10 months ago
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
15 years 5 months ago
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Memory and communication architectures have a significant impact on the cost, performance, and time-to-market of complex multi-processor system-on-chip (MPSoC) designs. The memory...
Sudeep Pasricha, Nikil D. Dutt
GIS
2000
ACM
15 years 3 months ago
A high-performance Web-based system design for spatial data accesses
With the increasing use of geographical data in real-world applications, Geographic Information Systems (GISs) have recently emerged as a fruitful area for research. Nowadays, a G...
Shu-Ching Chen, Xinran Wang, Naphtali Rishe, Mark ...
94
Voted
IPTPS
2003
Springer
15 years 4 months ago
Structured Peer-to-Peer Overlays Need Application-Driven Benchmarks
Considerable research effort has recently been devoted to the design of structured peer-to-peer overlays, a term we use to encompass Content-Addressable Networks (CANs), Distribut...
Sean C. Rhea, Timothy Roscoe, John Kubiatowicz