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HPCA
2012
IEEE
13 years 10 months ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev...
ISAAC
1999
Springer
110views Algorithms» more  ISAAC 1999»
15 years 7 months ago
Online Routing in Triangulations
We consider online routing algorithms for routing between the vertices of embedded planar straight line graphs. Our results include (1) two deterministic memoryless routing algorit...
Prosenjit Bose, Pat Morin
65
Voted
CORR
2010
Springer
64views Education» more  CORR 2010»
15 years 19 days ago
Opinion fluctuations and disagreement in social networks
ic copy available at: http://ssrn.com/abstract=1682187 Massachusetts Institute of Technology Department of Economics Working Paper Series Opinion Fluctuations and Disagreement in S...
Daron Acemoglu, Giacomo Como, Fabio Fagnani, Asuma...
PLDI
2006
ACM
15 years 9 months ago
SAFECode: enforcing alias analysis for weakly typed languages
Static analysis of programs in weakly typed languages such as C and C++ is generally not sound because of possible memory errors due to dangling pointer references, uninitialized ...
Dinakar Dhurjati, Sumant Kowshik, Vikram S. Adve
112
Voted
HPCA
2002
IEEE
16 years 3 months ago
The Minimax Cache: An Energy-Efficient Framework for Media Processors
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...
Osman S. Unsal, Israel Koren, C. Mani Krishna, Csa...