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136
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IEEEPACT
2002
IEEE
15 years 8 months ago
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
Jaewook Shin, Jacqueline Chame, Mary W. Hall
ICS
2010
Tsinghua U.
15 years 8 months ago
Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization
We explore the intersection between an emerging class of architectures and a prominent workload: GPGPUs (General-Purpose Graphics Processing Units) and regular expression matching...
Jamin Naghmouchi, Daniele Paolo Scarpazza, Mladen ...
131
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EUROSYS
2007
ACM
16 years 20 days ago
Tashkent+: memory-aware load balancing and update filtering in replicated databases
We present a memory-aware load balancing (MALB) technique to dispatch transactions to replicas in a replicated database. Our MALB algorithm exploits knowledge of the working sets ...
Sameh Elnikety, Steven G. Dropsho, Willy Zwaenepoe...
CGO
2008
IEEE
15 years 10 months ago
Automatic array inlining in java virtual machines
Array inlining expands the concepts of object inlining to arrays. Groups of objects and arrays that reference each other are placed consecutively in memory so that their relative ...
Christian Wimmer, Hanspeter Mössenböck
106
Voted
FPGA
2005
ACM
97views FPGA» more  FPGA 2005»
15 years 9 months ago
Techniques for synthesizing binaries to an advanced register/memory structure
Recent works demonstrate several benefits of synthesizing software binaries onto FPGA hardware, including incorporating hardware design into established software tool flows with m...
Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid