1000 search results - page 103 / 200 » Yield-Aware Cache Architectures |
121
Voted
INFOCOM
2010
IEEE
15 years 2 months ago
2010
IEEE
Abstract—Many network processing applications require wirespeed access to large data structures or a large amount of flowlevel data, but the capacity of SRAMs is woefully inadeq...
156
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JPDC
2010
15 years 2 months ago
2010
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
134
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IPPS
2010
IEEE
15 years 2 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
122
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HPCA
2003
IEEE
16 years 4 months ago
2003
IEEE
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications s...
119
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
We propose in this paper an algorithm for off-line selection of the contents of on-chip memories. The algorithm supports two types of on-chip memories, namely locked caches and sc...