Sciweavers

1000 search results - page 105 / 200
» Yield-Aware Cache Architectures
Sort
View
WMPI
2004
ACM
15 years 9 months ago
A compressed memory hierarchy using an indirect index cache
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
Erik G. Hallnor, Steven K. Reinhardt
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
15 years 10 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
ICCAD
2003
IEEE
131views Hardware» more  ICCAD 2003»
16 years 1 months ago
LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches
Leakage energy will be the major energy consumer in future deep sub-micron designs. Especially the memory sub-system of future SOCs will be negatively affected by this trend. In o...
Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel
SEMWEB
2007
Springer
15 years 10 months ago
A Caching Mechanism for Semantic Web Service Discovery
The discovery of suitable Web services for a given task is one of the central operations in Service-oriented Architectures (SOA), and research on Semantic Web services (SWS) aims a...
Michael Stollberg, Martin Hepp, Jörg Hoffmann
IPPS
2002
IEEE
15 years 9 months ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...