1000 search results - page 134 / 200 » Yield-Aware Cache Architectures |
117
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SIGMETRICS
2008
ACM
14 years 9 months ago
2008
ACM
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
100
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MICRO
2010
IEEE
14 years 8 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
RTAS
2010
IEEE
14 years 8 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
102
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ISCA
2012
IEEE
13 years 7 days ago
2012
IEEE
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
MICRO
2003
IEEE
15 years 3 months ago
2003
IEEE
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...