1000 search results - page 39 / 200 » Yield-Aware Cache Architectures |
108
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HPCA
1998
IEEE
15 years 6 months ago
1998
IEEE
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
133
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HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
164
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ISCA
2005
IEEE
15 years 7 months ago
2005
IEEE
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
114
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DAGSTUHL
2007
15 years 3 months ago
2007
The model-based transformation of loop programs is a way of detecting fine-grained parallelism in sequential programs. One of the challenges is to agglomerate the parallelism to a...
106
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ANCS
2009
ACM
14 years 11 months ago
2009
ACM
We propose MCRingBuffer, a lock-free, cache-efficient shared ring buffer that provides fast data accesses among threads running in multi-core architectures. MCRingBuffer seeks to ...