1000 search results - page 84 / 200 » Yield-Aware Cache Architectures |
SBACPAD
2009
IEEE
15 years 4 months ago
2009
IEEE
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
CLUSTER
2008
IEEE
15 years 4 months ago
2008
IEEE
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...
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ISPDC
2010
IEEE
14 years 8 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
ICMCS
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
ACSAC
2006
IEEE
15 years 3 months ago
2006
IEEE
Information leakage through covert channels and side channels is becoming a serious problem, especially when these are enhanced by modern processor architecture features. We show ...