Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardwar...
Ravi Bhargava, Ben Serebrin, Francesco Spadini, Sr...
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Large client-server data intensive applications can place high demands on system and network resources. This is especially true when the connection between the client and server s...
This paper presents an architecture for a persistent object store in which multi-level storage is explicitly included. Traditionally, DBMSs have assumed that all accessible data r...