711 search results - page 132 / 143 » Yield-aware placement optimization |
90
Voted
INFOVIS
2005
IEEE
15 years 5 months ago
2005
IEEE
The paper describes a novel technique to visualize graphs with extended node and link labels. The lengths of these labels range from a short phrase to a full sentence to an entire...
96
Voted
ISQED
2005
IEEE
15 years 5 months ago
2005
IEEE
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
92
Voted
ISPD
2005
ACM
15 years 5 months ago
2005
ACM
Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the g...
ATAL
2003
Springer
15 years 4 months ago
2003
Springer
In this paper we present a methodology for deciding the bidding strategy of agents participating in a significant number of simultaneous auctions, when finding an analytical sol...
FPGA
2003
ACM
15 years 4 months ago
2003
ACM
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...