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ASPDAC
2005
ACM
105views Hardware» more  ASPDAC 2005»
13 years 8 months ago
Interconnect estimation without packing via ACG floorplans
Abstract— ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a repre...
Jia Wang, Hai Zhou
ASPDAC
2005
ACM
87views Hardware» more  ASPDAC 2005»
13 years 12 months ago
Static power minimization in current-mode circuits
-We propose a method involvingselectivesignalgating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current ...
M. S. Bhat, H. S. Jamadagni
ASPDAC
2005
ACM
85views Hardware» more  ASPDAC 2005»
13 years 12 months ago
Integration of supercubing and learning in a SAT solver
Abstract— Learning is an essential pruning technique in modern SAT solvers, but it exploits a relatively small amount of information that can be deduced from the conflicts. Rece...
Domagoj Babic, Alan J. Hu
ASPDAC
2005
ACM
123views Hardware» more  ASPDAC 2005»
13 years 8 months ago
Yield driven gate sizing for coupling-noise reduction under uncertainty
Abstract— This paper presents a post-route gate-sizing algorithm for coupling-noise reduction that constrains the yield loss under process variations. Algorithms for coupling-noi...
Debjit Sinha, Hai Zhou
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
13 years 8 months ago
Feasibility analysis of messages for on-chip networks using wormhole routing
—The feasibility of a message in a network concerns if its timing property can be satisfied without jeopardizing any messages already in the network to meet their timing propert...
Zhonghai Lu, Axel Jantsch, Ingo Sander