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IEEEPACT
2007
IEEE
15 years 11 months ago
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...
Marek Olszewski, Jeremy Cutler, J. Gregory Steffan
IPPS
2007
IEEE
15 years 11 months ago
Experience of Optimizing FFT on Intel Architectures
Automatic library generators, such as ATLAS [11], Spiral [8] and FFTW [2], are promising technologies to generate efficient code for different computer architectures. The library...
Daniel Orozco, Liping Xue, Murat Bolat, Xiaoming L...
126
Voted
IPPS
2007
IEEE
15 years 10 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
15 years 10 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
132
Voted
ECOOP
2007
Springer
15 years 10 months ago
Aspect-Based Introspection and Change Analysis for Evolving Programs
— As new versions of software are developed bugs inevitably arise either due to regression or new functionality. Challenges arise in discovering, managing, and testing the impact...
Kevin J. Hoffman, Murali Krishna Ramanathan, Patri...