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DAC
2007
ACM
16 years 8 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2007
ACM
16 years 8 months ago
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting
The number and magnitude of process variation sources are increasing as we scale further into the nano regime. Today's most successful response surface methods limit us to lo...
Amith Singhee, Rob A. Rutenbar
DAC
2007
ACM
16 years 8 months ago
Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System
We consider the problem of optimizing the performance of a latency-insensitive system (LIS) where the addition of backpressure has caused throughput degradation. Previous works ha...
Rebecca L. Collins, Luca P. Carloni
DAC
2007
ACM
16 years 8 months ago
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
DAC
2007
ACM
16 years 8 months ago
Dynamic Power Management with Hybrid Power Sources
DPM (Dynamic Power Management) is an effective technique for reducing the energy consumption of embedded systems that is based on migrating to a low power state when possible. Whi...
Jianli Zhuo, Chaitali Chakrabarti, Kyungsoo Lee, N...
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