Verification is one of the most critical and time-consuming tasks in today's design processes. This paper demonstrates the verification process of a 8.8 million gate design u...
Johann Notbauer, Thomas W. Albrecht, Georg Niedris...
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
—Chemical–mechanical polishing (CMP) is an enabling technique used in deep-submicrometer VLSI manufacturing to achieve long range oxide planarization. Post-CMP oxide topography...
stract setting. Then we instantiate this algorithm with specific partial orderings and functions to obtain specific constraint propagation algorithms. In particular, using the noti...
Ordered Binary Decision Diagrams BDDs are a data structure for representation and manipulation of Boolean functions often applied in VLSI CAD. The choice of the variable orderin...