299 search results - page 24 / 60 » date 2003 |
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DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
As the technology is shrinking and the working frequency is going into multi gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically,...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
Envision the situation that high quality information and entertainment is easily accessible to anyone, anywhere, at any time, and on any device. How realistic is this vision? And ...