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ICCD
2004
IEEE
111views Hardware» more  ICCD 2004»
15 years 6 months ago
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Du...
MICRO
2010
IEEE
146views Hardware» more  MICRO 2010»
14 years 7 months ago
The ZCache: Decoupling Ways and Associativity
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
Daniel Sanchez, Christos Kozyrakis
PPAM
2005
Springer
15 years 3 months ago
A New Diagonal Blocking Format and Model of Cache Behavior for Sparse Matrices
Algorithms for the sparse matrix-vector multiplication (shortly SpM×V ) are important building blocks in solvers of sparse systems of linear equations. Due to matrix sparsity, the...
Pavel Tvrdík, Ivan Simecek
63
Voted
ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
15 years 1 months ago
The Block-Based Trace Cache
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
Bryan Black, Bohuslav Rychlik, John Paul Shen
87
Voted
OTM
2004
Springer
15 years 2 months ago
A Time Predictable Instruction Cache for a Java Processor
Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are diffi...
Martin Schoeberl