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FPGA
2000
ACM
120views FPGA» more  FPGA 2000»
15 years 1 months ago
A novel high throughput reconfigurable FPGA architecture
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial...
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, M...
FPGA
2000
ACM
125views FPGA» more  FPGA 2000»
15 years 1 months ago
Technology mapping for k/m-macrocell based FPGAs
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
Jason Cong, Hui Huang, Xin Yuan
APCCAS
2006
IEEE
227views Hardware» more  APCCAS 2006»
15 years 3 months ago
FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters
— We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-proce...
Arjuna Madanayake, Leonard T. Bruton
DATE
2000
IEEE
139views Hardware» more  DATE 2000»
15 years 1 months ago
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
FPL
2000
Springer
124views Hardware» more  FPL 2000»
15 years 1 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza