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ICES
2003
Springer
165views Hardware» more  ICES 2003»
15 years 2 months ago
Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms
This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor r...
Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Me...
FCCM
2003
IEEE
133views VLSI» more  FCCM 2003»
15 years 2 months ago
Floating Point Unit Generation and Evaluation for FPGAs
Most commercial and academic floating point libraries for FPGAs provide only a small fraction of all possible floating point units. In contrast, the floating point unit generat...
Jian Liang, Russell Tessier, Oskar Mencer
IPPS
2003
IEEE
15 years 2 months ago
Effective Utilization and Reconfiguration of Distributed Hardware Resources Using Job Management Systems
Reconfigurable hardware resources are very expensive, and yet can be underutilized. This paper describes a middleware capable of discovering underutilized computing nodes with FPG...
Kris Gaj, Tarek A. El-Ghazawi, Nikitas A. Alexandr...
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ISCAS
2003
IEEE
118views Hardware» more  ISCAS 2003»
15 years 2 months ago
Embedded reconfigurable array targeting motion estimation applications
Motion estimation is a complex computation found in video compression algorithms, such as standards like MPEG-4 and H.263. This paper proposes an embedded reconfigurable array for...
Sami Khawam, Tughrul Arslan, Fred Westall
ICCAD
2003
IEEE
219views Hardware» more  ICCAD 2003»
15 years 6 months ago
A Min-Cost Flow Based Detailed Router for FPGAs
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong