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ERSA
2006
119views Hardware» more  ERSA 2006»
14 years 12 months ago
Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment
Run-time assignment of a set of communicating tasks onto a heterogeneous multiprocessor system-on-chip (MPSoC) platform is a challenging task. Having FPGA fabric tiles in such MPS...
Vincent Nollet, Prabhat Avasare, Diederik Verkest,...
ERSA
2004
129views Hardware» more  ERSA 2004»
14 years 12 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
SAMOS
2007
Springer
15 years 4 months ago
An Evolutionary Approach to Area-Time Optimization of FPGA designs
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...
Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Paler...
ANCS
2007
ACM
15 years 2 months ago
Compiling PCRE to FPGA for accelerating SNORT IDS
Deep Payload Inspection systems like SNORT and BRO utilize regular expression for their rules due to their high expressibility and compactness. The SNORT IDS system uses the PCRE ...
Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan
70
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IPPS
2007
IEEE
15 years 4 months ago
A CAM Emulator Using Look-Up Table Cascades
An address table relates k different registered vectors to the addresses from 1 to k. An address generation function represents the address table. This paper presents a realizatio...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura