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2007
IEEE
85views Hardware» more  DATE 2007»
15 years 4 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
DSD
2007
IEEE
88views Hardware» more  DSD 2007»
15 years 4 months ago
An Implementation of an Address Generator Using Hash Memories
An address generator produces a unique address from 1 to k for the input that matches to one of k registered vectors, and produces 0 for other inputs. This paper presents the supe...
Tsutomu Sasao, Munehiro Matsuura
GLOBECOM
2007
IEEE
15 years 4 months ago
Agile Radio Implementation of OFDM Physical Layer for Dynamic Spectrum Access Research
In this paper we present the design process of an orthogonal frequency division multiplexing (OFDM) implementation for the Kansas University Agile Radio (KUAR). The KUAR is a porta...
Jordan D. Guffey, Alexander M. Wyglinski, Gary J. ...
GLOBECOM
2007
IEEE
15 years 4 months ago
A 10-Gbps High-Speed Single-Chip Network Intrusion Detection and Prevention System
Abstract—Network Intrusion Detection and Prevention Systems (NIDPSs) are vital in the fight against network intrusions. NIDPSs search for certain malicious content in network tr...
N. Sertac Artan, Rajdip Ghosh, Yanchuan Guo, H. Jo...
IPPS
2007
IEEE
15 years 4 months ago
Splice: A Standardized Peripheral Logic and Interface Creation Engine
Recent advancements in FPGA technology have allowed manufacturers to place general-purpose processors alongside user-configurable logic gates on a single chip. At first glance, ...
Justin Thiel, Ron K. Cytron