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CDES
2006
158views Hardware» more  CDES 2006»
15 years 1 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
ERSA
2003
137views Hardware» more  ERSA 2003»
15 years 1 months ago
Next Generation Architecture for Heterogeneous Embedded Systems
The Software Communications Architecture (SCA), a mandatory specification for Software Radio implementations by the Joint Tactical Radio System (JTRS), defines a Common Object R...
S. Murat Bicer, Frank Pilhofer, Graham Bardouleau,...
JCM
2007
95views more  JCM 2007»
15 years 6 days ago
Signal Canceller in the Carrier Super-positioning Satellite Networks
—To establish the interference canceller, generating replicas of unwanted carriers is a key. This paper addresses the design and performances of two types of signal canceller tha...
Mayumi Osato, Hiroyuki Kobashi, Robert Y. Omaki, T...
CODES
2007
IEEE
15 years 6 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid
DATE
2007
IEEE
104views Hardware» more  DATE 2007»
15 years 6 months ago
Dynamic reconfiguration in sensor networks with regenerative energy sources
In highly power constrained sensor networks, harvesting energy from the environment makes prolonged or even perpetual execution feasible. In such energy harvesting systems, energy...
Ani Nahapetian, Paolo Lombardo, Andrea Acquaviva, ...