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ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
14 years 3 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ICCAD
2008
IEEE
133views Hardware» more  ICCAD 2008»
14 years 3 months ago
Module locking in biochemical synthesis
—We are developing a framework for computation with biochemical reactions with a focus on synthesizing specific logical functionality, a task analogous to technology-independent...
Brian Fett, Marc D. Riedel
ICCAD
2008
IEEE
130views Hardware» more  ICCAD 2008»
14 years 21 days ago
Area-I/O flip-chip routing for chip-package co-design
— The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O’s in VLSI designs; it can achieve smaller package size, shorter wirelength, an...
Jia-Wei Fang, Yao-Wen Chang
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
14 years 3 months ago
Obstacle-avoiding rectilinear Steiner tree construction
— In today’s VLSI designs, there can be many blockages in a routing region. The obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem has become an important prob...
Liang Li, Evangeline F. Y. Young
ICCAD
2008
IEEE
122views Hardware» more  ICCAD 2008»
14 years 3 months ago
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Abstract— Power consumption has become a crucial problem in modern circuit design. Multiple Supply Voltage (MSV) design is introduced to provide higher flexibility in controllin...
Qiang Ma, Evangeline F. Y. Young