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ISCAS
2006
IEEE
15 years 6 months ago
2006
IEEE
In recent times, much attention has been devoted to power optimization for real-time systems, while guaranteeing that such systems meet their hard (or soft) scheduling deadlines. ...
96
Voted
ISCAS
2006
IEEE
15 years 6 months ago
2006
IEEE
Abstract- Analog iterative decoders offer several advantages over their digital counterparts in terms of speed and power -A- log-MAP consumption. The current state of art CMOS anal...
93
Voted
ISCAS
2006
IEEE
15 years 6 months ago
2006
IEEE
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
67
Voted
ISCA
2006
IEEE
15 years 6 months ago
2006
IEEE
We present a novel framework for defining memory models in terms of two properties: thread-local Instruction Reordering axioms and Store Atomicity, which describes inter-thread c...
106
Voted
ISCAS
2006
IEEE
15 years 6 months ago
2006
IEEE
– Increasing logic densities and clock frequencies on FPGAs lead to rapid increase in power density, which translates to higher on-chip temperature. In this paper, we investigate...