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173

GLVLSI
2007
IEEE

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I-cache multi-banking and vertical interleaving

15 years 9 months ago

I-cache multi-banking and vertical interleaving

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Sangyeun Cho

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92

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VLSI
2007
Springer

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Efficient DSP algorithm development for FPGA and ASIC technologies

15 years 9 months ago

Efficient DSP algorithm development for FPGA and ASIC technologies

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Shiv Balakrishnan, Chris Eddington

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88

GLVLSI
2007
IEEE

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Improvements for constraint solving in the systemc verification library

15 years 9 months ago

Improvements for constraint solving in the systemc verification library

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Daniel Große, Rüdiger Ebendt, Rolf Drec...

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90

GLVLSI
2007
IEEE

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Optimization techniques for BDD-based bisimulation computation

15 years 9 months ago

Optimization techniques for BDD-based bisimulation computation

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Ralf Wimmer, Marc Herbstritt, Bernd Becker

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105

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GLVLSI
2007
IEEE

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An asynchronous fpga logic cell implementation

15 years 7 months ago

An asynchronous fpga logic cell implementation

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Atabak Mahram, Mehrdad Najibi, Hossein Pedram

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