Sciweavers

HRI
2012
ACM
14 years 8 days ago
Enhancing interaction through exaggerated motion synthesis
Michael J. Gielniak, Andrea Lockerd Thomaz
HRI
2012
ACM
14 years 8 days ago
ROS and Rosbridge: roboticists out of the loop
The advent of ROS, the Robot Operating System, has finally made it possible to implement and use state-of-the-art navigation and manipulation algorithms on widely-available, inex...
Christopher Crick, Graylin Jay, Sarah Osentoski, O...
HRI
2012
ACM
14 years 8 days ago
How to use non-linguistic utterances to convey emotion in child-robot interaction
Vocal affective displays are vital for achieving engaging and effective Human-Robot Interaction. The same can be said for linguistic interaction also, however, while emphasis ma...
Robin Read, Tony Belpaeme
HPCA
2012
IEEE
14 years 8 days ago
Power balanced pipelines
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
John Sartori, Ben Ahrens, Rakesh Kumar
HPCA
2012
IEEE
14 years 8 days ago
System-level implications of disaggregated memory
Recent research on memory disaggregation introduces a new architectural building block—the memory blade—as a cost-effective approach for memory capacity expansion and sharing ...
Kevin T. Lim, Yoshio Turner, Jose Renato Santos, A...
HPCA
2012
IEEE
14 years 8 days ago
Decoupled dynamic cache segmentation
The least recently used (LRU) replacement policy performs poorly in the last-level cache (LLC) because temporal locality of memory accesses is filtered by first and second level...
Samira Manabi Khan, Zhe Wang, Daniel A. Jimé...
HPCA
2012
IEEE
14 years 8 days ago
Pacman: Tolerating asymmetric data races with unintrusive hardware
Data races are a major contributor to parallel software unreliability. A type of race that is both common and typically harmful is the Asymmetric data race. It occurs when at leas...
Shanxiang Qi, Norimasa Otsuki, Lois Orosa Nogueira...
HPCA
2012
IEEE
14 years 8 days ago
SCD: A scalable coherence directory with flexible sharer set encoding
Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain cache coherence. However, previously proposed coherence directories are hard to scale beyond...
Daniel Sanchez, Christos Kozyrakis
HPCA
2012
IEEE
14 years 8 days ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev...