112
Voted
MEMOCODE
2010
IEEE
15 years 8 days ago
2010
IEEE
Elastic systems provide tolerance to the variations in computation and communication delays. The incorporation of elasticity opens new opportunities for optimization using new corr...
186
click to vote
MEMOCODE
2010
IEEE
15 years 8 days ago
2010
IEEE
Abstract--This paper shows an implementation of CANSCID (Combined Architecture for Stream Categorization and Intrusion Detection). To satisfy the required system throughput, the pa...
138
click to vote
MEMOCODE
2010
IEEE
15 years 8 days ago
2010
IEEE
To overcome over-synchronization in synchronous programs, we recently introduced clock refinement to our synchronous programming language Quartz. This extension basically allows p...
127
Voted
MEMOCODE
2010
IEEE
15 years 8 days ago
2010
IEEE
Monitoring temporal SystemC properties is crucial for the validation of functional and transaction-level models, yet the current SystemC standard provides no support for temporal s...
99
Voted
MEMOCODE
2010
IEEE
15 years 8 days ago
2010
IEEE
This paper presents a working solution for the MEMOCODE 2010 design contest. The design presented in this paper is implemented in the Xilinx V5LX330 FPGA as a custom circuit. The s...
114
Voted
MEMOCODE
2010
IEEE
15 years 8 days ago
2010
IEEE
We present a modular approach for verification of synchronization behavior in concurrent programs that use reentrant locks. Our approach decouples the verification of the lock impl...
94
Voted
MEMOCODE
2010
IEEE
15 years 8 days ago
2010
IEEE
141
Voted
MEMOCODE
2010
IEEE
15 years 8 days ago
2010
IEEE
A new language, Feldspar, is presented, enabling high-level and platform-independent description of digital signal processing (DSP) algorithms. Feldspar is a pure functional langua...
107
click to vote
MEMOCODE
2010
IEEE
15 years 8 days ago
2010
IEEE
Design of critical embedded systems demands for guarantees on the reliability of the implementation/compilation of a specification. In general, this guarantee takes either the form...
136
click to vote
MEMOCODE
2010
IEEE
15 years 8 days ago
2010
IEEE
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...