138
Voted
ITC
1999
IEEE
16 years 3 days ago
1999
IEEE
189
Voted
ITC
1999
IEEE
16 years 3 days ago
1999
IEEE
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
142
Voted
ITC
1999
IEEE
16 years 3 days ago
1999
IEEE
151
Voted
ITC
1999
IEEE
16 years 3 days ago
1999
IEEE
179
Voted
ITC
1999
IEEE
16 years 3 days ago
1999
IEEE
SEMATECH has sponsored a "Test Method Evaluation" study to understand the trade-offs among the most common test methodologies used in the industry[1,2]. This paper prese...
177
Voted
ITC
1999
IEEE
16 years 3 days ago
1999
IEEE
Design diversity has long been used to protect redundant systems against common-mode failures. The conventional notion of diversity relies on "independent" generation of...
147
Voted
ITC
1999
IEEE
16 years 3 days ago
1999
IEEE
189
Voted
ITC
1999
IEEE
16 years 3 days ago
1999
IEEE
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...
153
Voted
ITC
1999
IEEE
16 years 3 days ago
1999
IEEE
Static Component Interconnection Test Technology (SCITT) is a new XNOR circuit based technology that is used for board-level interconnection test. SCITT provides an easy test meth...
193
click to vote
ITC
1999
IEEE
16 years 3 days ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...